module ddr_system_bd_ddr4_0_0 (
    input  sys_rst,
    input                 c0_sys_clk_p,
    input                 c0_sys_clk_n,
    output                c0_ddr4_act_n,
    output [16:0]          c0_ddr4_adr,
    output [1:0]          c0_ddr4_ba,
    output [1:0]          c0_ddr4_bg,
    output [1:0]          c0_ddr4_cke,
    output [1:0]          c0_ddr4_odt,
    output [1:0]          c0_ddr4_cs_n,
    output [0:0]               c0_ddr4_ck_t,
    output [0:0]               c0_ddr4_ck_c,
    output                c0_ddr4_reset_n,
    output                c0_ddr4_parity,
    inout  [71:0]          c0_ddr4_dq,
    inout  [17:0]         c0_ddr4_dqs_c,
    inout  [17:0]         c0_ddr4_dqs_t,
    output                c0_init_calib_complete,
    output                c0_ddr4_ui_clk,
    output                c0_ddr4_ui_clk_sync_rst,
    output               dbg_clk,
    output [63:0]       dbg_rd_data_cmp,
    output [63:0]       dbg_expected_data,
    output wire [2:0]   dbg_cal_seq,
    output wire [31:0]  dbg_cal_seq_cnt,
    output wire [7:0]   dbg_cal_seq_rd_cnt,
    output wire         dbg_rd_valid,
    output wire [5:0]   dbg_cmp_byte,
    output wire [63:0]  dbg_rd_data,
    output wire [15:0]  dbg_cplx_config,
    output wire [1:0]   dbg_cplx_status,
    output wire [27:0]  dbg_io_address,
    output wire         dbg_pllGate,
    output wire [19:0]  dbg_phy2clb_fixdly_rdy_low,
    output wire [19:0]  dbg_phy2clb_fixdly_rdy_upp,
    output wire [19:0]  dbg_phy2clb_phy_rdy_low,
    output wire [19:0]  dbg_phy2clb_phy_rdy_upp,
    output wire [127:0] cal_r0_status,
    output wire [8:0]   cal_post_status,
    input                              c0_ddr4_s_axi_ctrl_awvalid,
    output                             c0_ddr4_s_axi_ctrl_awready,
    input  [31:0]                      c0_ddr4_s_axi_ctrl_awaddr,
    input                              c0_ddr4_s_axi_ctrl_wvalid,
    output                             c0_ddr4_s_axi_ctrl_wready,
    input  [31:0]                      c0_ddr4_s_axi_ctrl_wdata,
    output                             c0_ddr4_s_axi_ctrl_bvalid,
    input                              c0_ddr4_s_axi_ctrl_bready,
    output [1:0]                       c0_ddr4_s_axi_ctrl_bresp,
    input                              c0_ddr4_s_axi_ctrl_arvalid,
    output                             c0_ddr4_s_axi_ctrl_arready,
    input  [31:0]                      c0_ddr4_s_axi_ctrl_araddr,
    output                             c0_ddr4_s_axi_ctrl_rvalid,
    input                              c0_ddr4_s_axi_ctrl_rready,
    output [31:0]                      c0_ddr4_s_axi_ctrl_rdata,
    output [1:0]                       c0_ddr4_s_axi_ctrl_rresp,
    output                             c0_ddr4_interrupt,
    input                 c0_ddr4_aresetn,
    input  [0:0]      c0_ddr4_s_axi_awid,
    input  [33:0]    c0_ddr4_s_axi_awaddr,
    input  [7:0]                       c0_ddr4_s_axi_awlen,
    input  [2:0]                       c0_ddr4_s_axi_awsize,
    input  [1:0]                       c0_ddr4_s_axi_awburst,
    input  [0:0]                       c0_ddr4_s_axi_awlock,
    input  [3:0]                       c0_ddr4_s_axi_awcache,
    input  [2:0]                       c0_ddr4_s_axi_awprot,
    input  [3:0]                       c0_ddr4_s_axi_awqos,
    input                              c0_ddr4_s_axi_awvalid,
    output                             c0_ddr4_s_axi_awready,
    input  [255:0]    c0_ddr4_s_axi_wdata,
    input  [31:0]  c0_ddr4_s_axi_wstrb,
    input                              c0_ddr4_s_axi_wlast,
    input                              c0_ddr4_s_axi_wvalid,
    output                             c0_ddr4_s_axi_wready,
    input                              c0_ddr4_s_axi_bready,
    output [0:0]      c0_ddr4_s_axi_bid,
    output [1:0]                       c0_ddr4_s_axi_bresp,
    output                             c0_ddr4_s_axi_bvalid,
    input  [0:0]      c0_ddr4_s_axi_arid,
    input  [33:0]    c0_ddr4_s_axi_araddr,
    input  [7:0]                       c0_ddr4_s_axi_arlen,
    input  [2:0]                       c0_ddr4_s_axi_arsize,
    input  [1:0]                       c0_ddr4_s_axi_arburst,
    input  [0:0]                       c0_ddr4_s_axi_arlock,
    input  [3:0]                       c0_ddr4_s_axi_arcache,
    input  [2:0]                       c0_ddr4_s_axi_arprot,
    input  [3:0]                       c0_ddr4_s_axi_arqos,
    input                              c0_ddr4_s_axi_arvalid,
    output                             c0_ddr4_s_axi_arready,
    input                              c0_ddr4_s_axi_rready,
    output [0:0]      c0_ddr4_s_axi_rid,
    output [255:0]    c0_ddr4_s_axi_rdata,
    output [1:0]                       c0_ddr4_s_axi_rresp,
    output                             c0_ddr4_s_axi_rlast,
    output                             c0_ddr4_s_axi_rvalid,
    output wire [511:0]             dbg_bus
);
assign c0_init_calib_complete = sys_rst;
assign c0_ddr4_s_axi_ctrl_awready = 1'b0;
assign c0_ddr4_s_axi_ctrl_wready = 1'b0;
assign c0_ddr4_s_axi_ctrl_bvalid = 1'b0;
assign c0_ddr4_s_axi_ctrl_arready = 1'b0;
assign c0_ddr4_s_axi_ctrl_rvalid = 1'b0;
assign c0_ddr4_s_axi_awready = 1'b0;
assign c0_ddr4_s_axi_wready = 1'b0;
assign c0_ddr4_s_axi_bvalid = 1'b0;
assign c0_ddr4_s_axi_arready = 1'b0;
assign c0_ddr4_s_axi_rvalid = 1'b0;
endmodule
